Raspberry Pi – RP2350 MCU

With the release of the RP2040 microcontroller, Raspberry Pi began offering their own custom-designed ICs. The development team in Cambridge followed this up with the RP1, a PCIe interface bridge utilised in the Raspberry Pi 5.

Now, the new RP2350 MCU has been introduced, a significant upgrade over the RP2040 in many respects.

The RP2350 continues the dual-core design, and with the derivatives RP2354A/B, Raspberry Pi will for the first time be offering controllers with integrated flash memory. For a quick start or seamless integration into your application, Raspberry Pi Pico 2 boards will soon be available.

RP2350 – More Performance and Features

Raspberry Pi has integrated not only two ARM Cortex-M33 cores into the RP2350 but also two RISC-V Hazard3 cores. The primary clock speed is rated up to 150MHz. However, the RP2350 remains a dual-core MCU, meaning only two cores can be active at any given time. The choice of active cores can be set either via software or by using the on-chip OTP memory.

The RP2350 includes 520kB of SRAM but does not feature integrated flash. However, external flash memory or PSRAM can be connected via the XIP unit using a QSPI interface.

The universal PIO, introduced with the RP2040, has been made even more efficient and powerful in this iteration. As the use of PIO can be a complex topic, Raspberry Pi has dedicated an entire chapter to this flexible peripheral in the Raspberry Pi Pico-series C/C++ SDK documentation, which goes far beyond the standard interface implementations (UART, I2C, PWM, SPI, etc.) found in the datasheet. This allows developers to get creative when implementing interfaces using PIO.

For better power management, the RP2350 now includes five power domains, which can be turned off depending on the mode being used.

In terms of security, Raspberry Pi has equipped the RP2350 with features such as SecureBoot (verification of binaries via signature checks) and Encrypted Boot (with OTP in the RP2350 containing the keys for decrypting binaries when loaded into SRAM). The ARMv8 architecture of the Cortex-M33 also brings with it SAU and MPU regions, which enable the separation of secure and non-secure code.

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